Efficient Synchronization for a Large-scale Multi-core Chip Architecture

Multi-core architectures are becoming mainstream, permitting increasing on-chip parallelism through hardware support for multithreading. Synchronization, especial finegrain synchronization, is essential to the effective utilization of the computational power of high-performance large-scale multi-core architectures. However, designing and implementing fine-grain synchronization in such architectures presents several challenges, including issues of synchronization induced overhead, storage cost, scalability, and the level of granularity to which synchronization is applicable. Using the 160-core IBM Cyclops-64 multi-core chip architecture as a case study, this dissertation first presents a thorough performance measurement, evaluation, and customization of a range of widely used synchronization mechanisms. This dissertation then proposes Synchronization State Buffer (SSB), a scalable architectural design for fine-grain synchronization that efficiently enforces word-level mutual exclusion and read-after-write data-dependencies between concurrent threads. The design of SSB is motivated by the following simple observation: at any instance during the parallel execution only a small fraction of memory locations are actively participating in synchronization. Based on this observation we present a fine-grain synchronization design that records and manages the states of frequently synchronized data using modest hardware support. We have implemented SSB design in the context of the IBM Cyclops-64 architecture. Using detailed simulation, the experimental results demonstrate significant performance gain due to the use of SSB-based fine-grain synchronization solution for a set of selected benchmarks with different workload characteristics.